High performance read bypass test for SRAM circuits

ABSTRACT

A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of an SRAM array, and a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode without impacting performance, and bypass the read output of the SRAM array and allow a test signal to pass though in a test mode.

BACKGROUND

1. Technical Field

The present invention relates to a design structure. More specifically,it relates a design structure for high performance SRAM (Static RandomAccess Memory) read bypass for the built-in self-test.

2. Background Information

Built-in self-test (BIST) is a mechanism used within an integratedcircuit (IC) to verify all or a portion of the internal functionality ofthe IC. BIST can reduce the duration of an IC manufacturing test, and,by reducing the number of input/output signals that must be driven orexamined under tester control, reduce the complexity of the test setup.Hence, BIST can effectively reduce the cost of IC manufacturing tests.BIST can also be designed to perform field-diagnostics of individualdevices or entire systems. For example, it can used to perform aself-diagnostic test for a computer peripheral device (e.g. a printer)at its power-up.

Logic BIST (LBIST) is one type of BIST technology, which is designed fortesting random logic. Some LBIST interfaces for SRAM arrays require theability to test downstream chip logic by bypassing the functional outputof the array, and inserting test signals into the SRAM array read outputpath. FIG. 1 is a diagram illustrating components of a LBIST interface.In FIG. 1, the components for functional output of the SRAM arrayinclude an SRAM Dynamic Output unit 101 and a Dynamic to StaticConversion unit 103. A Static Test Logic Unit 102 is used for testpurposes. To bypass the functional output, a control unit 104 needs tobe implemented. FIG. 1 illustrates a common method of accomplishing theSRAM bypass, in which a multiplexer (the Test Mux 104) is used at theoutput of the Dynamic to Static Conversion unit 103, and a test signalfrom the Static Test Logic unit 102 is used to select static test data.

However, when using a multiplexer to bypass the functional output of anSRAM array, extra circuitry is required to be added to the criticaloutput path for SRAM operations, and thus results in an increased delay.

SUMMARY

A design structure embodied in a machine readable medium used in adesign process and an integrated circuit for high performance SRAM(Static Random Access Memory) read bypass for the built-in self-test.The design structure and integrated structure includes a dynamic tostatic conversion unit for a read output of an SRAM array, and a testbypass unit integrated into the dynamic to static conversion unit, so asto allow the read output of the SRAM array to pass through in a non-testmode, and block the read output of the SRAM array and allow a testsignal to pass though in a test mode.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram of a conventional read path dynamic-to-staticconversion and static test bypass configuration.

FIG. 2 is a diagram of the configuration with integrateddynamic-to-static conversion and test bypass (DSC-TB) unit in oneembodiment of the present invention.

FIG. 3 is a circuit diagram illustrating the structure of the DSC-TBunit in one embodiment of the present invention.

FIG. 4 is a waveform illustrating the operation of the DSC-TB unit inthe functional mode.

FIG. 5 is a waveform illustrating the operation of the DSC-TB unit inthe test mode.

FIG. 6 is a flow diagram of a design process used in semiconductordesign, manufacture, and/or test.

DETAILED DESCRIPTION

The invention will now be described in more detail by way of examplewith reference to the embodiments shown in the accompanying Figures. Itshould be kept in mind that the following described embodiments are onlypresented by way of example and should not be construed as limiting theinventive concept to any particular physical configuration.

Further, if used and unless otherwise stated, the terms “upper,”“lower,” “front,” “back,” “over,” “under,” and similar such terms arenot to be construed as limiting the invention to a particularorientation. Instead, these terms are used only on a relative basis.

The present invention is directed to a mechanism to integrate the LBISTtest function into the hold path of the dynamic to static conversionunit, thus removing load from the critical path and improving overallperformance.

FIG. 2 is a diagram illustrating the configuration with integrateddynamic-to-static conversion and test bypass in one embodiment of thepresent invention.

As illustrated in FIG. 2, in one embodiment of the present invention,the traditional LBIST test bypass logic (e.g. the Test Mux 104 inFIG. 1) is removed from the critical path. The present invention has anSRAM Dynamic Output unit 201 for functional output and a Static TestLogic unit 202 for testing. The SRAM Dynamic Output unit 201 can be thesame as the SRAM Dynamic Output unit 101 in FIG. 1, and the Static testLogic unit 202 can be the same as the Static Test Logic unit 102 inFIG. 1. A Dynamic to Static Conversion with Test Bypass (DSC-TB) unit200 is used to both perform the dynamic to static conversion and bypassthe functional output, when the respective work mode is chosen. Since noextra circuitry in the critical output path is needed to control theoutput flow in the testing mode, the overall performance will beimproved. An integrated DSC-TB unit 200 will not negatively affect thepower consumption, nor will it add burden to its size constraints.

According to one embodiment of the present invention, the DSC-TB unit200 is created by modifying the Dynamic to Static Conversion unit 103 intwo ways. The Dynamic to Static Conversion unit 103 is implemented byusing a standard cross-coupled device. To build a DSC-TB unit 200, oneextra leg and a complex gate hold buffer (as shown in FIG. 3) are addedto the Dynamic to Static Conversion unit 103. The test function is thusimplemented in the hold path, so that the original test structure 104from the critical path can be removed.

FIG. 3 is a circuit diagram illustrating the structure of the DSC-TBunit 200 in one embodiment of the present invention.

In FIG. 3, devices T12-T15 constitute the top half of the DSC-TB unit200, which is a normal cross-coupled device, as the one used in theDynamic to Static Conversion unit 103. Devices T0-T2 and T6-T8constitute a hold buffer. The hold buffer is connected to the clock(‘clk’) equivalent leg of the cross-coupled device (T12-T15), thusmaking the cross-couple device (T12-T15) a latch, and controls the stateof the latch. Therefore, this circuit can work in both a functional modeand a test mode (as describe below). By choosing the test mode, thecircuit can switch from a functional mode to a test mode to realize thebuilt-in self test. It can feed test data (‘tq’) through thecross-coupled device (T12-T15) during this operation, and effectively“bypass” the input from the SRAM array. Devices T3-T5 and T9-T11constitute the bottom half of the DSC-TB unit 200, which uses a complexgate implementation. Devices T3-T5 and T9-T11 are designed to isolatethe ‘xnand’ signal, and select test data ‘tq’, when working in the testmode. In an alternate embodiment of the present invention, across-coupled nor implementation may be used instead of thecross-coupled nand implementation. The cross-coupled nor implementationwill use the same number of devices in slightly altered order, but theDSC-TB and the devices will operate in the same manner.

According to one embodiment of the present invention, the DSC-TB unit200 can operate in two modes:

1. The Functional Mode

This is the normal mode of operation, in which the ‘test’ signal is heldlow and the circuit operates as a normal cross-coupled device.

In the functional mode, the circuit is capable of reading one bit fromthe array per cycle, and when needed, it can also hold data for multiplecycles until the next read operation takes place. A ‘precharge’ signal(‘pchg’) is typically used for precharging a data line and other dynamicsignals, but in this circuit its main role is to define the timings ofthe capture and hold state of the latch. With the ‘test’ signal heldlow, the ‘hold’ signal becomes the inversion of the ‘pchg’ signal, andthe devices T4 and T10 connected by the ‘test’ signal becometransparent. Thus, the device operates as a conventional CCNAND(Cross-Coupled Not And) circuit, where the ‘hold’ signal acts as theclocking/controlling signal. Therefore, when the ‘pchg’ signal is low,the ‘hold’ signal is high, and then the cross-coupled device is in a“hold” state. However, when the ‘pchg’ signal rises, the pre-chargedevice T8 turns off, the ‘hold’ signal becomes low, and the deviceenters a “capture” state in which it accepts the data input (i.e. the‘d_b’ signal). The output ‘q’ signal of the DSC-TB unit 200 isindependent of any inputs of the unit, when the ‘pchg’ signal remainslow (i.e. in the “hold” state) and the ‘test’ signal remains low (i.e.the unit is in the “functional” mode). In the functional mode, the inputsignal for testing, ‘tq’, is gated as long as the ‘test’ signal remainslow, and plays no role in this mode.

A waveform of the functional mode operation of the DSC-TB unit 200 canbe seen in FIG. 4.

FIG. 4 illustrates two read cycles—a cycle of reading ‘0’ followed by acycle of reading ‘1’. In the functional mode, the ‘test’ signal willremain low (not shown in FIG. 4). The ‘hold’ signal is the inversion ofthe ‘pchg’ signal. The output signal ‘q’ follows the data input signal‘d_b’ during the “capture” state when the ‘pchg’ signal is high. Theoutput signal ‘q’ will remain if it is in the “hold” mode when the‘pchg’ signal is low. For example, the ‘d_b’ signal turns high at timeT1, but the ‘q’ signal remains low because the ‘pchg’ signal is lowduring that period of time, and hence the circuit is in the “hold” mode.The ‘tq’ input signal (not shown in FIG. 4) is gated in this operationalmode. The output signal ‘q’ is independent of the test input signal‘tq’.

2. The Test Mode

The DSC-TB unit 200 enters the test mode whenever the ‘test’ signal isheld high. In one embodiment of the present invention, in the test mode,the ‘pchg’ signal is kept low to force the cross-coupled device into its“hold” state, and to pre-charge the functional ‘d_b’ input. In this“hold” state, a low ‘pchg’ signal effectively forces the gate connectedto the ‘pchg’ devices (T2 and T8 in FIG. 3) to be transparent. The‘hold’ signal is then an inversion of the ‘tq’ input. When the ‘test’signal is high, the ‘xnand’ signal is isolated by device T10, and the‘xnand_b’ signal becomes an inversion of the ‘hold’ signal. While the‘d_b’ signal held high, the second gate (T15 in FIG. 3) in thecross-coupled device causes an inversion of the ‘xnand_b’ signal.Therefore, the output signal ‘q’ follows the original static testinginput signal ‘tq’. In this embodiment, the ‘pchg’ signal is always lowin test mode. The device input signal ‘d_b’ is thus held high and playsno role.

In alternative embodiments of the present invention, the ‘pchg’ signalmay be held high. A ‘pchg’ signal toggled to high would force the ‘hold’signal to be low, the ‘xnand_b’ signal to be high, the ‘xnand’ signal tobe low, and, ultimately, the ‘q’ signal to be high. This may be usefulwhen a high output signal is preferred in an application. Similarly, inanother embodiment of the present invention, the ‘d_b’ signal may betoggled in the test mode.

FIG. 5 illustrates a waveform of the DSC-TB unit in the test mode.

In the test mode, the ‘pchg’ signal is kept low (not shown in FIG. 5).When the ‘test’ signal is high, the output signal ‘q’ follows the testinput signal ‘tq’. The ‘hold’ signal is the inversion of the ‘tq’signal. In this example, data input signal ‘d_b’ is always high (nowshown in FIG. 5), and the output ‘q’ is independent of the data inputfrom ‘d_b’.

FIG. 6 shows a block diagram of an exemplary design flow 600 used forexample, in semiconductor design, manufacturing, and/or test. Designflow 600 may vary depending on the type of IC being designed. Forexample, a design flow 600 for building an application specific IC(ASIC) may differ from a design flow 600 for designing a standardcomponent. Design structure 620 is preferably an input to a designprocess 610 and may come from an IP provider, a core developer, or otherdesign company or may be generated by the operator of the design flow,or from other sources. Design structure 620 comprises an embodiment ofthe invention as shown in FIG. 2-FIG. 5 in the form of schematics orHDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.).Design structure 620 may be contained on one or more machine-readablemedium. For example, design structure 620 may be a text file or agraphical representation of an embodiment of the invention as shown inFIG. 2-FIG. 5. Design process 610 preferably synthesizes (or translates)an embodiment of the invention as shown in FIG. 2-FIG. 5 into a netlist680, where netlist 680 is, for example, a list of wires, transistors,logic gates, control circuits, I/O, models, etc. that describes theconnections to other elements and circuits in an integrated circuitdesign and recorded on at least one of machine readable medium. This maybe an iterative process in which netlist 680 is re-synthesized one ormore times depending on design specifications and parameters for thecircuit.

Design process 610 may include using a variety of inputs; for example,inputs from library elements 630 which may house a set of commonly usedelements, circuits, and devices, including models, layouts, and symbolicrepresentations, for a given manufacturing technology (e.g., differenttechnology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 640,characterization data 650, verification data 660, design rules 670, andtest data files 685 (which may include test patterns and other testinginformation). Design process 610 may further include, for example,standard circuit design processes such as timing analysis, verification,design rule checking, place and route operations, etc. One of ordinaryskill in the art of integrated circuit design can appreciate the extentof possible electronic design automation tools and applications used indesign process 610 without deviating from the scope and spirit of theinvention. The design structure of the invention is not limited to anyspecific design flow.

Design process 610 preferably translates an embodiment of the inventionas shown in FIG. 2-FIG. 5, along with any additional integrated circuitdesign or data (if applicable), into a second design structure 690.Design structure 690 resides on a storage medium in a data format usedfor the exchange of layout data of integrated circuits (e.g. informationstored in a GDSII (GDS2), GLI, OASIS, or any other suitable format forstoring such design structures). Design structure 690 may compriseinformation such as, for example, test data files, design content files,manufacturing data, layout parameters, wires, levels of metal, vias,shapes, data for routing through the manufacturing line, and any otherdata required by a semiconductor manufacturer to produce an embodimentof the invention as shown in FIG. 2-FIG. 5. Design structure 690 maythen proceed to a stage 695 where, for example, design structure 690:proceeds to tape-out, is released to manufacturing, is released to amask house, is sent to another design house, is sent back to thecustomer, etc.

While the invention has been particularly shown and described withreference to specific embodiment thereof, it should be understood,however, that the invention is not necessarily limited to the specificprocess, arrangement, materials and components shown and describedabove, but may be susceptible to numerous variations within the scope ofthe invention. For example, although the above-described exemplaryaspects of the invention are believed to be particularly well suited forhigh performance read bypass test circuit, it is contemplated that theconcepts of the present invention can be applied in other applications.For example, the concepts of the present application can be utilizedwhenever it is desired to perform bypass test. The circuits andprocesses described herein may be represented (without limitation) insoftware (object code or machine code), in varying stages ofcompilation, as one or more netlists, in a simulation language, in ahardware description language, by a set of semiconductor processingmasks, and as partially or completed realized semiconductor devices. Thevarious alternatives for each of the foregoing as understood by those ofskill in the art are also within the scope of this invention. Forexample, the various types of computer-readable media, softwarelanguages (e.g. Verilog, VHDL), simulatable representations (e.g. SPICEnetlist), semiconductor processes (e.g. CMOS, GaAs, SiGe, etc), anddevice types (e.g. FPGA) suitable for using in conjunction with theprocesses described herein are within the scope of the invention.

It will be apparent to one skilled in the art that the manner of makingand using the claimed invention has been adequately disclosed in theabove-written description taken together with the drawing.

Finally, although various advantages, aspects, and objects of thepresent invention have been discussed herein with reference to variousembodiments, it will be understood that the scope of the inventionshould not be limited by the reference to such advantages, aspects, andobjects. Rather, the scope of the invention should be determined withreference to the appended claims.

1. A design structure embodied in a machine readable medium used in adesign process, the design structure comprising: a dynamic to staticconversion unit for a read output of an SRAM array; and a test bypassunit integrated into the dynamic to static conversion unit, so as toallow the read output of the SRAM array to pass through in a non-testmode, without affecting functional performance of the dynamic to staticconversion unit, and block the read output of the SRAM array and allow atest signal to pass though in a test mode.
 2. The design structure ofclaim 1, wherein the dynamic to static conversion unit comprises across-coupled device.
 3. The design structure of claim 2, wherein theintegrated test bypass unit comprises a hold buffer that is connected toa clock equivalent leg of the cross-coupled device to control workingmodes of the bypass unit.
 4. The design structure of claim 3, wherein atest signal is sent to the hold buffer and the cross coupled device tochoose between a functional mode and a test mode for the dynamic tostatic conversion unit.
 5. The design structure of claim 2, wherein theintegrated test bypass unit comprises a complex gate implementation thatis connected to the cross-coupled device to select a test input as anoutput of the dynamic to static conversion unit.
 6. The design structureof claim 1, wherein the design structure comprises a netlist.
 7. Thedesign structure of claim 1, wherein the design structure resides on astorage medium as a data format for the exchange of layout data ofintegrated circuits.
 8. The design structure of claim 1, wherein thedesign structure includes at least one of test data, characterizationdata, verification data, or design specification.
 9. An integratedcircuit for high performance SRAM (Static Random Access Memory) readbypass for chip logic testing, comprising: a dynamic to staticconversion unit for a read output of an SRAM array; and a test bypassunit integrated into the dynamic to static conversion unit, so as toallow the read output of the SRAM array to pass through in a non-testmode, without affecting functional performance of the dynamic to staticconversion unit, and block the read output of the SRAM array and allow atest signal to pass though in a test mode.
 10. The integrated circuit ofclaim 9, wherein the dynamic to static conversion unit comprises across-coupled device.
 11. The integrated circuit of claim 9, wherein thetest bypass unit comprises a hold buffer that is connected to a clockequivalent leg of the cross-coupled device to control working modes ofthe bypass unit.
 12. The integrated circuit of claim 11, wherein a testsignal is sent to the hold buffer and the cross coupled device to choosebetween a functional mode and a test mode for the dynamic to staticconversion unit.
 13. The integrated circuit of claim 9, wherein theintegrated test bypass unit comprises a complex gate implementation thatis connected to the cross-coupled device to select a test input as anoutput of the dynamic to static conversion unit.
 14. A method for highperformance SRAM (Static Random Access Memory) read bypass for chiplogic testing, comprising: providing a dynamic to static conversion unitfor a read output of an SRAM array; and providing a test bypass unitintegrated into the dynamic to static conversion unit, so as to allowthe read output of the SRAM array to pass through in a non-test mode,without affecting functional performance of the dynamic to staticconversion unit, and block the read output of the SRAM array and allow atest signal to pass though in a test mode.
 15. The method of claim 14,wherein the dynamic to static conversion unit comprises a cross-coupleddevice.
 16. The method of claim 14, wherein the test bypass unitcomprises a hold buffer that is connected to a clock equivalent leg ofthe cross-coupled device to control working modes of the bypass unit.17. The method of claim 16, wherein a test signal is sent to the holdbuffer and the cross coupled device to choose between a functional modeand a test mode for the dynamic to static conversion unit.
 18. Themethod of claim 14, wherein the integrated test bypass unit comprises acomplex gate implementation that is connected to the cross-coupleddevice to select a test input as an output of the dynamic to staticconversion unit.